Memory cell array and method for manufacturing it

ABSTRACT

In a storage cell array, a first and a second line are provided which have a crossing point, at which a storage element with magnetoresistive effect is disposed. A yoke is provided which surrounds one of the lines and that contains magnetizable material with a permeability of at least 10. The yoke is disposed in such a way that a magnetic flow is closed substantially through the storage element.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of copending InternationalApplication No. PCT/DE99/02402, filed Aug. 2, 1999, which designated theUnited States.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a memory cell array having memory elements withmagnetoresistive effect and a method for manufacturing it.

Technologie Analyse XMR-Technologien, Technologie-früh-erkennung[Technology Analysis XMR Technologies, Early Recognition of Technology],by Stefan Mengel, Publisher VDI-Technologiezentrum PhysikalischeTechnologie, discloses layered structures with magnetoresistive effect.Depending on its design, the layered structure is classified as a GMR(giant magnetoresistance) element, TMR (tunneling magnetoresitive)element, AMR (anisotropic resistance) element or CMR (colossalmagnetoresistance) element. The term GMR element is used in the art todesignate layered structures which have at least two ferromagneticlayers and a nonmagnetic, conductive layer arranged between them andexhibit the GMR (giant magnetoresistance) effect, that is to say exhibita large magnetoresistive effect in comparison with the AMR (anisotropicmagnetoresistance) effect. The GMR effect is understood as referring tothe fact that the electrical resistance of the GMR element is dependenton whether the magnetizations in the two ferromagnetic layers areoriented in parallel or antiparallel both for currents which areparallel (CIP current in plane) and perpendicular (CPP currentperpendicular to plane) to the layer planes. The resistance changes hereas a function of the orientation of the magnetizations by ΔR/R=5 percentto 20 percent at room temperature.

The term TMR element is used in the specialist field for “TunnelingMagnetoresistance” layered structures which have at least twoferromagnetic layers and an insulating, nonmagnetic layer arrangedbetween them. The insulating layer has such a small thickness that atunnel current occurs between the two ferromagnetic layers. These leadstructures also exhibit a magnetoresistive effect which is brought aboutby spin-polarized tunnel current through the insulating, nonmagneticlayer arranged between the two ferromagnetic layers. In this case also,the electrical resistance of the TMR element (CPP arrangement) isdependent on whether the magnetizations in the two ferromagnetic layersare oriented in parallel or antiparallel. The resistance varies byΔR/R=10 percent to approximately 30 percent at room temperature.

The AMR effect is due to the fact that the resistance in magnetizedconductors parallel to the magnetization direction varies from that ofmagnetized conductors which are perpendicular to the magnetizationdirection. It is a volume effect and thus occurs in ferromagnetic singlelayers.

A further magnetoresistive effect which is referred to as colossalmagnetoresistance effect due to its magnitude (ΔR/R=100 percent to 400percent at room temperature) requires a high magnetic field forswitching between the magnetization states owing to its high coercitiveforces.

It has been proposed (see for example D. D. Tang, P. K. Wang, V. S.Speriosu, S. Le, K. K. Kung, “Spin Valve RAM Cell”, IEEE Transactions onMagnetics, Vol. 31, No. 6, November 1996, page 3206) to use GMR elementsas memory elements in a memory cell array. The magnetization directionof the one ferromagnetic layer of the GMR element is held here, forexample, by an adjacent antiferromagnetic layer. Intersecting x and ylines are provided. In each case a memory element is arranged at thepoints of intersection of the x/y lines. In order to write information,the x/y lines are supplied with signals which bring about at the pointof intersection a magnetic field which is sufficient for the change ofpolarity. In order to read out the information, the x/y lines can besupplied with a signal which switches the respective memory cell to andfro between the two magnetization states. The current through the memoryelement from which the resistance value, and thus the information, isdetermined is measured.

In order to write and read, local magnetic fields of 10 Oe toapproximately 100 Oe corresponding to 8 A/cm to 80 A/cm are necessary.It is desirable here for the magnetic fields to be generated by thesmallest possible current in the lines.

However, as miniaturization progresses, the current densities necessaryto generate the local magnetic fields become greater. In addition, aneffect has been observed (see M. H. Kryder, Kie Y. Ahn, N. J. Mazzeo, S.Schwarzl, and S. M. Kane, “Magnetic Properties and Domain Structures inNarrow NiFe Stripes”, IEEE Transactions on Magnetics, Vol. Mag.-16, No.1, January 1980, page 99), in which the magnetic switching fieldthresholds increase as the dimensions become smaller, that is to sayhigher currents become necessary for switching.

SUMMARY OF THE INVENTION

It is accordingly an object of the invention to provide a memory cellarray and a method for manufacturing the memory cell array whichovercomes the above-mentioned disadvantageous of the prior art memorycell arrays and methods for producing arrays of this general type. Inparticular, it is an object of the invention to provide a memory cellarray having a memory element with magnetoresistive effect which can beprogrammed with lower currents and current densities than in the priorart.

With the foregoing and other objects in view there is provided, inaccordance with the invention a memory cell array, that includes: asubstrate having a main face; a first insulating layer configured on themain face of the substrate, the first insulating layer formed with atrench having a bottom and edges; a first line configured in the trenchof the first insulation layer; a second line; a memory elementconfigured at a point of intersection between the first line and thesecond line, the memory element being switched between the first lineand the second line; a first yoke disposed adjacent the bottom and theedges of the trench of the first insulation layer, the first yokeconfigured such that a magnetic flux through the first yoke isessentially closed in the memory element, the first yoke including amagnetizable material with a relative permeability of at least 10; and aline selected from the group consisting of the first line and the secondline being supplied with current during a write access and beingpartially surrounded by the first yoke.

In other words, at least a first line, a second line and a memoryelement with magnetoresistive effect which is arranged at a point ofintersection between the first line and the second line are provided inthe memory cell array. Preferably, the memory element is switchedbetween the first line and the second line. In addition, a yoke isprovided which partially surrounds at least one of the lines and whichcontains magnetizable material with a relative permeability of at least10. The yoke is arranged in such a way that the magnetic flux paththrough the yoke is closed essentially by means of the memory element.In order to write to the memory cell, the first line and the second lineare supplied with current in such a way that superposition of themagnetic fields of the first line and of the second line at the locationof the memory element generates a magnetic field which exceeds theswitching threshold of the memory element.

The yoke is magnetized here by the magnetic field of the line throughwhich current flows, the line being partially surrounded by the yoke. Asa result, the induction flux density B is increased by a factor μ_(r),the relative permeability. As a result, magnetic poles are produced atthe end faces of the yoke and a magnetic field is generated between thepoles. This magnetic field assumes very high values depending on theselection of the material of the yoke and is used to switch the memoryelement. Given identical current density in the line, considerablyhigher magnetic fields are thus achieved for switching the memoryelement.

Part of the yoke can be formed from all ferromagnetic and ferromagneticmaterials.

The yoke is preferably formed from soft-magnetic, ferromagnetic layers,in particular composed of Fe, Ni, Co, Mn, MnBi, FeSi—, FeNi—, FeCo—,FeAl— alloys or soft-magnetic ferrites.

The use of a magnetic flux concentrator in a memory cell array hasadmittedly already been proposed in U.S. Pat. No. 4,455,626. In thepublication a layer in which the magnetization is changed as a functionof the information from two adjacent write lines is used as a memoryelement. In order to read out the information, a magnetoresistive sensoris provided which is arranged below the storage layer together with aread line in the gap of a planar layer, designated as a magnetic shieldconcentrator, made of magnetizable material. The magnetic flux of thestorage layer is concentrated on the magnetoresistive sensor by thismagnetic field concentrator. The arrangement is not intended or suitablefor increasing the effectiveness of the currents in the linear writelines for the reversal of the polarity of the magnetic storage layer.

All known TMR elements and GMR elements in a CPP arrangement (currentperpendicular to plane) are suitable as a memory element in the memorycell array according to the invention. The GMR effect is greater if thecurrent flows perpendicular through the layer stack (CPP) than if thecurrent flows in parallel in the layers (CIP current in plane).Furthermore, all XMR elements which have at least two magnetizationstates with respectively different resistances that can be obtained byapplying a magnetic field whose strength can be tolerated by the memoryarray are suitable for being switched to and fro. In particular, the useof CMR elements is possible because the necessary magnetic fieldstrengths can be obtained by means of the yoke.

The memory elements preferably each have two ferromagnetic layers and anonmagnetic, insulating layer (TMR) or conductive layer (GMR) arrangedbetween them. The ferromagnetic layers each have two magnetizationstates. It is advantageous to use an insulating, nonmagnetic layer (TMRelement) because this enables higher element resistances (≧100 KΩ) to beobtained and these are more favorable in terms of the power consumptionand signal-to-noise ratio.

One of the ferromagnetic layers is preferably arranged adjacent to anantiferromagnetic layer which fixes the magnetization direction in theadjacent ferromagnetic layer. Materials suitable for theantiferromagnetic layer are, inter alia, materials containing at leastone of the elements Fe, Mn, Ni, Cr, Co, V, Ir, Tb and O.

As an alternative, the memory elements can each have two ferromagneticlayers and a nonmagnetic layer arranged between them. One of theferromagnetic layers is magnetically harder than the other ferromagneticlayer, that is to say, the polarity of only one ferromagnetic layer isreversed, while the other remains unaffected. The nonmagnetic layer maybe insulating or noninsulating.

Alternatively, the two ferromagnetic layers are essentially of the samemagnetization composition, it being possible to selectively switch overthe polarity of the magnetization in one of the ferromagnetic layers bymeans of the yoke.

Suitable materials for the ferromagnetic layers are, inter alia, thosewhich contains at least one of the element Fe, Ni, Co, Cr, Mn, Gd, Dy.The thickness of the ferromagnetic layers in GMR elements in a CIParrangement is preferably in the range between 2 and 10 nm. In GMR andTMR elements in a CPP arrangement, the thickness of the ferromagneticlayers may also be greater (for example 100 to 200 nm). Al₂O₃, MgO, NiO,HfO₂, TiO₂, NbO or SiO₂ are suitable as the insulating material for thenonmagnetic layer which acts as a tunnel insulator. Cu or Ag aresuitable as the noninsulating material for the nonmagnetic layer. Thethickness of the nonmagnetic layer is in the range between 1 and 4 nm,preferably between 2 and 3 nm.

The memory elements preferably have dimensions in the range between 0.05μm and 20 μm. They can be, inter alia, of square or elongated shape.

The lines, the memory element and the yoke are preferably containedintegrated in a substrate. It is particularly advantageous to use asubstrate which includes a carrier wafer, in particular made ofsemiconductor material, particularly monocrystalline silicon, because inthis case the integrated memory cell array can be manufactured with themethods of silicon processing technology. As a result, a high packingdensity can be achieved in the memory cell array. Furthermore, theperiphery can also be integrated in the substrate.

According to one refinement of the invention, the substrate on thecarrier wafer has a first insulating layer which is provided with atrench. The first line runs in the trench. The memory element isarranged above the first line and the second line is arranged above thememory element. The yoke partially surrounds either the first line orthe second line. If the yoke partially surrounds the first line, itadjoins the sides and the floor of the trench and can be manufactured bymeans of layer deposition after the formation of the trench in the firstinsulating layer. If the yoke surrounds the second line, it adjoins thesides and the surface of the second line facing away from the memoryelement and can be manufactured by layer deposition and spacer etchings.

Preferably, a first yoke and a second yoke are provided which are eachembodied like the yoke. The first yoke partially surrounds the firstline and the second yoke partially surrounds the second line. Both thefirst yoke and the second yoke are arranged in such a way that amagnetic flux path through the first yoke or the second yoke is closedessentially by means of the memory element. This configuration has theadvantage that both the magnetic field generated by the first linethrough which current flows and the magnetic field generated by thesecond line through which current flows bring about a reinforcedmagnetic field at the location of the memory element by means of thefirst yoke or the second yoke respectively.

In the memory cell array, the memory cell is selected by means of thefirst line and the second line between which the memory element isswitched. The routing of the first line and of the second line withrespect to one another can be both parallel and perpendicular to oneanother in the vicinity of the memory element. Accordingly, the magneticfields which are oriented in parallel or magnetic fields which areoriented perpendicularly to one another are superposed at the locationof the memory element.

In order to achieve high storage densities it is advantageous to providea multiplicity of memory elements with a yoke, first lines and secondlines. The memory elements, which are preferably arranged in a grid, areeach arranged at a point of intersection between one of the first linesand one of the second lines.

Because local magnetic fields which are considerably higher, at least bya factor of 10 to 100, are generated in the memory cell array accordingto the invention for a given current strength, considerably lowercurrent densities occur in the lines with the same line cross section.The necessary current densities are below the limit defined byelectromigration, even given a high degree of miniaturization of thememory cell array.

Because increased local magnetic fields can be achieved with the samecurrent strength, magnetically harder layers, which have a substantiallyhigher coercitive field strength than 10 Oe, may also be used for thememory element. Memory elements made of magnetically harder layers havethe advantage that they are less sensitive to external magneticinterference. As a result, less stringent requirements are made on themagnetic field shielding. In addition, the risk of data loss is reduced.

As a result of the lower current densities, it is not necessary toincrease the level of the lines, and thus the aspect ratios. The memorycell array is therefore also suitable for stacked arrays in order toincrease the storage density.

Due to the lower current strength which is necessary to generate thesame magnetic field, the power consumption can be reduced considerablyduring the writing and reading operations.

With the foregoing and other objects in view there is also provided, inaccordance with the invention a method for manufacturing a memory cellarray, that includes steps of: applying a first insulating layer to acarrier wafer; producing a trench having side walls and a bottom in thefirst insulating layer; producing a first yoke that adjoins the sidewalls of the trench and that adjoins the bottom of the trench, andproducing the first yoke from a magnetizable material with apermeability of at least 10; producing a first line in the trench;producing a memory element with magnetoresistive effect above the firstyoke and connecting the memory element to the first line; and producinga second line above the memory element and connecting the second line tothe memory element.

In accordance with an added mode of the invention, in order to producethe first yoke, a second insulating layer having a trench formed withedges is produced. Spacers are formed on the edges of the trench formedin the second insulating layer, and the spacers are made of amagnetizable material with a permeability of at least 10. The methodwould also include steps of: producing the second line in the trenchformed in the second insulating layer; producing a yoke part from amagnetizable material with a permeability of at least 10; and producingthe yoke part to partially cover the second line above the memoryelement and connecting the yoke part to the spacers such that thespacers and the yoke part form a second yoke.

In accordance with another mode of the invention, the method includessteps of: in order to produce the first yoke, applying a secondinsulating layer on the carrier wafer; producing a trench having edgesin the second insulating layer; forming spacers, made of a magnetizablematerial with a permeability of at least 10, on the edges of the trenchin the second insulating layer; producing the second line in the trenchin the second insulating layer; producing a yoke part from amagnetizable material with a permeability of at least 10; and producingthe yoke part to partially cover the second line above the memoryelement and connecting the yoke part to the spacers such that thespacers and the yoke part form a second yoke.

In accordance with a concomitant mode of the invention, the methodincludes steps of: forming a line selected from the group consisting ofthe first line and the second line by depositing a metal layer and byperforming chemical-mechanical polishing.

Other features which are considered as characteristic for the inventionare set forth in the appended claims.

Although the invention is illustrated and described herein as embodiedin a memory cell array and method for manufacturing it, it isnevertheless not intended to be limited to the details shown, sincevarious modifications and structural changes may be made therein withoutdeparting from the spirit of the invention and within the scope andrange of equivalents of the claims.

The construction and method of operation of the invention, however,together with additional objects and advantages thereof will be bestunderstood from the following description of specific embodiments whenread in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1a shows a section through a memory element that is switchedbetween a first line and a second line, and that has a yoke partiallysurrounding one of the lines;

FIG. 1b shows a section through the yoke illustrated in FIG. 1a;

FIG. 2a shows a memory element which is switched between a first lineand a second line, and that has a yoke partially surrounding the firstline;

FIG. 2b shows a section through the yoke shown in FIG. 2a and thestorage element;

FIG. 3 shows a section through a substrate after trench etching withdeposition of a ferromagnetic layer;

FIG. 4 shows the section through the substrate illustrated in FIG. 3after formation of a first yoke and a first line in the trench;

FIG. 5 shows the section through the substrate illustrated in FIG. 4after formation of a first ferromagnetic layer which is surrounded by aninsulating layer;

FIG. 6a shows the section through the substrate illustrated in FIG. 5after formation of a tunnel layer and a second ferromagnetic layer;

FIG. 6b shows the section designated in FIG. 6a by b—b after depositionof an insulating layer and formation of a second trench (The sectionillustrated in FIG. 6a is designated by a—a in FIG. 6b);

FIG. 7 shows the section illustrated in FIG. 6b after the formation ofspacers and a second line above the second ferromagnetic layer;

FIG. 8 shows the section through the substrate illustrated in FIG. 7after formation of a cover layer above the second line, which, togetherwith the spacers, forms a second yoke; and

FIG. 9 Shows a detail of a memory cell array which has magnetoresistiveelements as memory elements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to the figures of the drawing in detail and first,particularly, to FIG. 1a thereof, there is shown a memory element SEwith magnetoresistive effect that is arranged between a first line L1,for example made of AlCu, and a second line L2, for example made fromAlCu. The memory element SE is electrically connected both to the firstline L1 and to the second line L2. The first line L1 and the second lineL2 run perpendicularly to one another. The memory element SE is arrangedat the point of intersection between the first line L1 and the secondline L2.

The second line L2 is partially surrounded by a yoke J (see FIG. 1a).The yoke J includes an upper part J1, two lateral parts J2 and two lowerparts J3. The upper part J1 adjoins that surface of the second line L2which faces away from the memory element SE. The lateral parts J2 adjointhe upper part J1 and the side walls of the second line L2. The lowerparts J3 adjoin the lateral parts J2 and the part of the surface of thesecond line L2 which is adjacent to the memory element SE. The yoke J isformed from iron. Furthermore, all the soft ferromagnetic elements suchas Fe, FeNi, Ni, Co or similar are suitable. The thickness D of theupper part J1 perpendicular to the plane extending through the firstline L1 and the second line L2, and the comparable thickness of thelateral parts J2 parallel to the plane extending from L1 and L2 areapproximately 20 percent of the width of the line L2. The thickness d ofthe lower parts J3 perpendicular to the plane extending from the firstline L1 and the second line L2 is at least equal to the thickness of thememory element SE, at maximum approximately 20 percent of the width ofthe conductor track L2 (see FIG. 1b).

If a current flows through the second line L2, a magnetic field H isgenerated outside the line L2. This magnetic field generates in the yokeJ a magnetic flux Φ=μ_(o)μ_(r) H which is approximately constant in themagnetic circuit. In the upper part J1 of the yoke, the magnetic fluxΦ=μ_(o)μ_(r) f H, f=D b being the cross sectional face of the yoke partsJ1 and J2, and b the extent of the yoke J perpendicular to the plane ofthe drawing. In the lower parts J3 of the yoke J the magnetic fluxΦ=μ_(o)μ_(r) F H, F=d b being the cross sectional face of the parts J3.The lower parts J3 of the yoke J have magnetic poles on the end faceswhich face one another. A magnetic field H_(a) for which the followingapproximately applies owing to the constancy of the magnetic flux:H_(a)=μ_(r) F/f H is generated between the magnetic poles P. Because, onthe other hand, the maximum achievable magnetic field strength insoft-magnetic material is determined, in the case of saturation, by thesaturation magnetization M_(s) of the pole shoe material, the followingapplies: H_(a)=F/f(H+M_(s))≈(F/f)M_(s). In comparison with thesaturation magnetization M_(s), the magnetic field H, which is of theorder of the magnitude of 10 to 100 A/cm, is usually negligible.

Iron has a saturation induction of μ_(o)M_(s) (M_(s): saturationmagnetization)=2.1 T. The maximum achievable magnetic field strengthH_(a) is thus 1.67×10⁶ A/m (21 koe) if F/f equals 1. In this statementit has been assumed that the leakage field losses between the lowerparts J3 of the yoke J and the memory element SE are negligible.

A memory element SE′ with magnetoresistive effect is switched between afirst line L1′ and a second line L2′ (see FIG. 2a). The first line L1′is partially surrounded by a yoke J′. The yoke J′ has a lower part J1′and two lateral parts J2′. Perpendicular to the plane extending throughthe first line L1′ and the second line L2′, the lower part J1′ of theyoke J′ has a thickness D of approximately 20 percent of the width ofthe line L1′ (see FIG. 2b). The thickness of the memory element SE′perpendicular to the plane passing through the first line L1′ and thesecond line L2′ is d=20 nm to approximately 100 nm.

If a current flows through the first line L1′, a magnetic field H isproduced which brings about a magnetic flux Φ in the yoke J′ and thememory element SE′. As a result the memory element can be switched as afunction of the sign of the current. In the same way as in the exemplaryembodiment explained with reference to FIGS. 1a and 1b, in thisexemplary embodiment which is to be preferred in terms of production, acomparable reinforcement and concentration of the magnetic fieldgenerated by the conductor current is produced at the location of thememory element SE′.

This concentrated variant results in inhomogeneous magnetizationdistributions in the memory element in the edge areas which adjoin theyoke J2′. These do not adversely affect the switching effect, but mustbe taken into account during reading out.

The manufacture of a memory cell array for a 0.18 μm technology will bedescribed below with reference to FIGS. 3 to 8.

A first insulating layer 2 made of SiO₂ is applied to a carrier wafer 1made of monocrystalline silicon. The first insulating layer 2 has athickness of 300 to 400 nm. A first trench 3 is produced in the firstinsulating layer 2 using photolithographic process steps. The firsttrench 3 has a depth of 200 to 300 nm, a width of 250 to 300 nm and alength, dependent on the cell field, of 50 μm to 400 μm.

Subsequently, a first soft-magnetic layer 4 made of Fe or permalloy(Ni₈₀Fe₂₀) is deposited to a layer thickness of 20 to 60 nm. Thethickness of the first soft-magnetic layer 4 is approximately 10 to 20percent of the width of the first trench 3. The deposition can becarried out by sputtering, vapor deposition, CVD, electroplating or thelike (see FIG. 3). The first soft-magnetic layer 4 is structuredtransversely to the direction of the first trench 3 usingphotolithographic process steps and anisotropic etching, so that it hasa strip intersecting the first trench 3.

By depositing a metalization layer which contains AlCu and fills up theregion of the first trench 3 completely, and by subsequentchemical-mechanical polishing a first line 5 is formed, and a first yoke4′ is formed by structuring the first soft-magnetic layer 4. The extentof the first yoke 4′ perpendicular to the plane of the drawing isdetermined by the proceeding structuring and is 200 to 300 nm. Thechemical-mechanical polishing stops as soon as the surface of the firstinsulating layer 2 is exposed (see FIG. 4).

A thin insulation layer 6 made of Sio₂ is deposited over the entiresurface to a layer thickness of 20 to 60 nm and is structured usingphotolithographic process steps in such a way that the surface of thefirst line 5 is partially exposed. A first ferromagnetic layer 7 issubsequently generated by deposition and chemical-mechanical polishing.The first ferromagnetic layer 7 fills up the opening in the insulationlayer 6. The first ferromagnetic layer 7 is electrically connected tothe first line 5 (see FIG. 5). The thickness of the ferromagnetic layer7 is 20 to 40 nm, the width is 180 to 200 nm and the depth perpendicularto the plane of the drawing is 180 to 200 nm (see FIG. 5). The firstferromagnetic layer 7 is insulated from the first yoke 4′.

A tunnel barrier layer 8 made of Al₂O₃ is formed on the surface of thefirst ferromagnetic layer 7 by reactive sputtering a 2 to 4 nm thickaluminum oxide layer (Al₂O₃) (not shown on drawing).

The first ferromagnetic layer 7 is formed from Co (or anotherferromagnetic material).

A second ferromagnetic layer 9 is formed on the surface of the tunnellayer by deposition and photolithographic structuring. The secondferromagnetic layer 9 is formed from Co. It has a thickness of 20 to 60nm, a width of 180 to 200 nm and a depth transversely to the path of thefirst line 5 of 200 to 300 nm (see FIG. 6a and FIG. 6b).

A second insulating layer 10 made of SiO₂ is deposited to a layerthickness of 200 to 300 nm. A second trench 11 is produced in the secondinsulating layer 10 using photolithographic process steps. The surfaceof the second ferromagnetic layer 9 is at least partially exposed on thebottom of the second trench 11. The second trench 11 has a width of 200to 300 nm, a depth of 200 to 300 nm and a length perpendicular to therouting of the first line 5 of 50 to 400 μm.

Spacers 12 are formed on the edges of the second trench 11 by depositinga second soft-magnetic layer made of Fe or Ni₈₀Fe₂₀ and anisotropicetching back. The width of the spacers 12 is 20 to 60 nm. It isdetermined by the thickness of the deposited second low-reactivitylayer.

A second line 13 is formed in the second trench 11 by depositing ametalization layer which has AlCu and a thickness of 200 to 400 nm, andsubsequent chemical-mechanical polishing which stops at the surface ofthe second insulating layer 10 made of SiO₂. The second line 13 fillsthe second trench 11 completely (see FIG. 7). A yoke part 14 whose crosssection corresponds essentially to the cross section of the secondferromagnetic layer 9 is formed on the surface of the second line 13 bydepositing a third soft-magnetic layer of 20 to 60 nm and structuringusing photolithographic process steps. The yoke part 14 and the spacers12 together form a second yoke which partially surrounds the second line13. The second yoke reinforces the magnetic field generated by thesecond line 13 through which current flows, at the location of thesecond ferromagnetic layer 9.

The first yoke 4′ reinforces the magnetic field which is generated bythe first line 5 through which current flows.

The first line 5 and the second line 13 are connected by means of amemory element which is formed from the first ferromagnetic layer 7, thetunnel layer 8 and the second ferromagnetic layer 9 and which exhibits amagnetoresistive effect. The resistance of the memory element can bemeasured by appropriately driving the first line 5 and the second line13. In this way, the information stored in the various magnetizationstates is read out.

To write information, the first line 5 and the second line 13 are drivenin such a way that the magnetic field at the location of the secondferromagnetic layer 9, resulting from the current flow, is sufficient tochange the magnetization state of the second ferromagnetic layer 9.Because of the different material properties, the magnitude and/or theferromagnetic layer 7, 9, the magnetization state of the firstferromagnetic layer 7 remains unchanged here.

To form a memory cell array which has magnetoresistive elements andmemory cells S, the memory elements S are arranged in a grid (see FIG.9). Each memory element S is switched here between a first line Le1 anda second line Le2. The first lines Le1 run parallel to one another andintersect the second lines Le2 which also run parallel to one another.

1. A memory cell array, comprising: a substrate having a main face; afirst insulating layer configured on said main face of said substrate,said first insulating layer formed with a trench having a bottom andedges; a first line configured in said trench of said first insulationlayer; a second line; a memory element configured at a point ofintersection between said first line and said second line, said memoryelement being switched between said first line and said second line; afirst yoke disposed adjacent said bottom and said edges of said trenchof said first insulation layer, said first yoke configured such that amagnetic flux through said first yoke is essentially closed in saidmemory element, said first yoke including a magetizable magnetizablematerial with a relative permeability of at least 10; and a lineselected from the group consisting of said first line and said secondline being supplied with current during a write access and beingpartially surrounded by said first yoke.
 2. The memory cell arrayaccording to claim 1, wherein said first yoke includes a soft-magnetic,ferromagnetic material.
 3. The memory cell array according to claim 2,wherein: said first line has a surface; said substrate includes acarrier wafer with a main face defining said main face of saidsubstrate; and said memory element is configured above said first yokeand on said surface of said first line.
 4. The memory cell arrayaccording to claim 2, wherein: said substrate includes a carrier waferwith a main face defining said main face of said substrate; said secondline is configured above said memory element and has edges and a surfacefacing away from said memory element; and comprising: a second yokeconfigured above said memory element and adjacent said edges of saidsecond line and adjacent said surface of said second line facing awayfrom said memory element; and a second insulating layer partiallysurrounding said second line and said second yoke.
 5. The memory cellarray according to claim 4, wherein said memory element is configuredabove said first yoke and said first line.
 6. The memory cell arrayaccording to claim 1, comprising a second yoke configured above saidmemory element and configured such that a magnetic flux through saidsecond yoke is essentially closed in said memory element; said secondyoke including a magnetizable material with a relative permeability ofat least
 10. 7. The memory cell array according to claim 1, comprising:a plurality of first lines disposed parallel to each other; a pluralityof second lines disposed parallel to each other; and a plurality ofconfigurations each including a memory element and at least one yokepartially surrounding a line selected from the group consisting of oneof said plurality of said first lines and one of said plurality of saidsecond lines, said at least one yoke configured such that a magneticflux through said at least one yoke is essentially closed by said memoryelement, said at least one yoke including a magnetizable material with arelative permeability of at least 10; said memory element being switchedbetween a pair of states with a line selected from the group consistingone of said plurality of said first lines and one of said plurality ofsaid second lines.
 8. The memory cell array according to claim 7,wherein each one of said configurations includes a further yokepartially surrounding a different line selected from the groupconsisting of the one of said plurality of said first lines and the oneof said plurality of said second lines; said further yoke configuredsuch that a magnetic flux through said further yoke is essentiallyclosed by said memory element, said further yoke including amagnetizable material with a relative permeability of at least
 10. 9.The memory cell array according to claim 1, wherein said memory elementincludes at least one element or material selected from the groupconsisting of Fe, Ni, Co, Cr, Mn, Gd, Dy, Al₂O₃, NiO, HfO₂, TiO₂, NbO,and SiO₂; and said first yoke includes at least one element selectedfrom the group consisting of Fe, Ni, Co, Cr, Mn, Gd, and Dy.
 10. Amethod for manufacturing a memory cell array, which comprises: applyinga first insulating layer to a carrier water; producing a trench havingside walls and a bottom in the first insulating layer; producing a firstyoke that adjoins the side walls of the trench and that adjoins thebottom of the trench, and producing the first yoke from a magnetizablematerial with a permeability of at least 10; producing a first line inthe trench; producing a memory element with magnetoresistive effectabove the first yoke and connecting the memory element to the firstline; producing a second line above the memory element and connectingthe second line to the memory element; insuring that the memory elementis configured at a point of intersection between the first line and thesecond line; switching the memory element between the first line and thesecond line; configuring the first yoke such that a magnetic fluxthrough the first yoke is essentially closed in the memory element;during a write access, supplying current to a given line selected from agroup consisting of the first line and the second line; and partiallysurrounding the given line with the first yoke.
 11. The method accordingto claim 10, which comprises: in order to produce the first yoke,producing a second insulating layer having a trench formed with edges;forming spacers made of a magnetizable material with a permeability ofat least 10 on the edges of the trench formed in the second insulatinglayer; producing the second line in the trench formed in the secondinsulating layer; producing a yoke part from a magnetizable materialwith a permeability of at least 10; and producing the yoke part topartially cover the second line above the memory element and connectingthe yoke part to the spacers such that the spacers and the yoke partform a second yoke.
 12. The method according to claim 10, whichcomprises forming a line selected from the group consisting of the firstline and the second line by depositing a metal layer and by performingchemical-mechanical polishing.
 13. The method according to claim 12,which comprises: in order to produce the first yoke, applying a secondinsulating layer on the carrier wafer; producing a trench having edgesin the second insulating layer; forming spacers, made of a magnetizablematerial with a permeability of at least 10, on the edges of the trenchin the second insulating layer; producing the second line in the trenchin the second insulating layer; producing a yoke part from amagnetizable material with a permeability of at least 10; and producingthe yoke part to partially cover the second line above the memoryelement and connecting the yoke part to the spacers such that thespacers and the yoke part form a second yoke.
 14. The method accordingto claim 13, which comprises forming a line selected from the groupconsisting of the first line and the second line by depositing a metallayer and by performing chemical-mechanical polishing.